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-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:41:12 11/20/2011 
-- Design Name: 
-- Module Name:    latch_MEMWB - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity latch_MEMWB is
	port (
			iRegWD	: in  std_ulogic_vector(15 downto 0);
			oRegWD	: out std_ulogic_vector(15 downto 0);
			
			iRegWA	: in  std_ulogic_vector(3 downto 0);
			oRegWA	: out std_ulogic_vector(3 downto 0);
			
			clk    : in std_ulogic;
			rst    : in std_ulogic;
			enable : in std_ulogic
		 );
end latch_MEMWB;

architecture Behavioral of latch_MEMWB is
    component latch16
        port (
            i      : in  std_ulogic_vector(15 downto 0);
            o      : out std_ulogic_vector(15 downto 0);
            clk    : in  std_ulogic;
            rst    : in  std_ulogic;
            enable : in  std_ulogic
            );
    end component;
    component latch4
        port (
            i      : in  std_ulogic_vector(3 downto 0);
            o      : out std_ulogic_vector(3 downto 0);
            clk    : in  std_ulogic;
            rst    : in  std_ulogic;
            enable : in  std_ulogic
            );
    end component;
    component latch6
        port (
            i      : in  std_ulogic_vector(5 downto 0);
            o      : out std_ulogic_vector(5 downto 0);
            clk    : in  std_ulogic;
            rst    : in  std_ulogic;
            enable : in  std_ulogic
            );
    end component;
begin
	U_REGWD: latch16 port map(iRegWD, oRegWD, clk, rst, enable);
	U_REGWA: latch4  port map(iRegWA, oRegWA, clk, rst, enable);
end Behavioral;

